RBRINTEN=DISABLE_THE_RDA_INTE, ABTOINTEN=DISABLE_AUTO_BAUD_TI, MSINTEN=DISABLE_THE_MS_INTER, RLSINTEN=DISABLE_THE_RLS_INTE, THREINTEN=DISABLE_THE_THRE_INT, ABEOINTEN=DISABLE_END_OF_AUTO_
Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)
| RBRINTEN | RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt. 0 (DISABLE_THE_RDA_INTE): Disable the RDA interrupt. 1 (ENABLE_THE_RDA_INTER): Enable the RDA interrupt. |
| THREINTEN | THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5]. 0 (DISABLE_THE_THRE_INT): Disable the THRE interrupt. 1 (ENABLE_THE_THRE_INTE): Enable the THRE interrupt. |
| RLSINTEN | Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1]. 0 (DISABLE_THE_RLS_INTE): Disable the RLS interrupt. 1 (ENABLE_THE_RLS_INTER): Enable the RLS interrupt. |
| MSINTEN | Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR. 0 (DISABLE_THE_MS_INTER): Disable the MS interrupt. 1 (ENABLE_THE_MS_INTERR): Enable the MS interrupt. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| ABEOINTEN | Enables the end of auto-baud interrupt. 0 (DISABLE_END_OF_AUTO_): Disable end of auto-baud Interrupt. 1 (ENABLE_END_OF_AUTO_B): Enable end of auto-baud Interrupt. |
| ABTOINTEN | Enables the auto-baud time-out interrupt. 0 (DISABLE_AUTO_BAUD_TI): Disable auto-baud time-out Interrupt. 1 (ENABLE_AUTO_BAUD_TIM): Enable auto-baud time-out Interrupt. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |